Issues

• No clock signals being traced inside testbench module

  vproc/vicuna#133 · Filter by author pah69 opened on Mar 12, 2026
  1

• How to handle "30525: Illegal instruction (hart 0) at PC 0x0000208c: 0x304022f3"?

  vproc/vicuna#123 · Filter by author deeplearner92 opened on Sep 12, 2024
  2

• How to Handle conv + bias in conv_3x3 for input(int8) * weight(int8) + bias(int32)?

  vproc/vicuna#122 · Filter by author Haleski47 opened on Jul 30, 2024

• Applications hang indefinitely on Verilator when size of data cache is different than 0

  vproc/vicuna#121 · Filter by author maheshejs opened on Jan 4, 2024
  1

• Certain applications when executed with dual and triple pipeline configurations on verilated model of Vicuna hang indefinittely

  vproc/vicuna#119 · Filter by author AnjaliVerma1314 opened on Nov 28, 2023

• Machine mode CSRs not accessible with Ibex host core when using Vicuna's verilated model

  vproc/vicuna#118 · Filter by author AnjaliVerma1314 opened on Nov 28, 2023
  3

• Error in Questasim Simulation

  vproc/vicuna#114 · Filter by author aaqdas opened on Jul 26, 2023

• 'Illegal Instruction' when executing sign and zero extend functions when destination LMUL=8

  vproc/vicuna#112 · Filter by author ParkerJones567 opened on Jul 3, 2023

• Combinatorial Loop Alert while Generating bitstream for vicuna using CV32E40X as a scalar core

  vproc/vicuna#111 · Filter by author Nikhil-311293 opened on May 5, 2023
  4

• Floating point support.

  vproc/vicuna#110 · Filter by author Nikhil-311293 opened on Mar 16, 2023

• No way to clear a cache error?

  vproc/vicuna#105 · Filter by author stevobailey opened on Sep 24, 2022

• Vicuna + Ibex and WFI

  vproc/vicuna#104 · Filter by author stevobailey opened on Aug 11, 2022

• narrowing instructions are never popped from the instruction queue

  vproc/vicuna#103 · Filter by author moimfeld opened on Aug 11, 2022
  1

• Wrong operand for vwmacc(u|us|su).vx

  vproc/vicuna#102 · Filter by author moimfeld opened on Aug 11, 2022

• Wrong result generated by multiply unit (probably control logic related)

  vproc/vicuna#101 · Filter by author moimfeld opened on Aug 9, 2022
  1

• vslidedown.(vx|vi) issue when VLMAX is exceeded

  vproc/vicuna#99 · Filter by author moimfeld opened on Aug 8, 2022

• Masking not working

  vproc/vicuna#98 · Filter by author moimfeld opened on Aug 8, 2022

• Tail-undisturbed policy violation for comparison instructions.

  vproc/vicuna#97 · Filter by author moimfeld opened on Aug 8, 2022

• Rounding issue for vasub(u).(vv|vx)

  vproc/vicuna#96 · Filter by author moimfeld opened on Aug 8, 2022

• Suggestion for vectorizing MaxPool and Convolution Layer

  vproc/vicuna#95 · Filter by author Mousavikia opened on Jul 26, 2022
  1

• Error in Synthesizing the vicuna on Genesys2 board

  question
  vproc/vicuna#91 · Filter by author Nikhil-311293 opened on Jul 7, 2022
  4

• Illegal configuration created by config.mk

  bug
  vproc/vicuna#89 · Filter by author moimfeld opened on Jun 27, 2022
  2

• Verilator problem in simulating added custom config

  vproc/vicuna#86 · Filter by author Mousavikia opened on Jun 17, 2022

• Rare infinite stall triggered by a specific delay constellation during memory transactions

  bug
  vproc/vicuna#85 · Filter by author moimfeld opened on Jun 15, 2022
  1

• Tail-agnostic policy violation for mask instruction

  bug
  vproc/vicuna#79 · Filter by author moimfeld opened on Jun 9, 2022
  1