Issues

• Feedback request: ran biRISC-V through a new local RTL checker (results inside)

  ultraembedded/biriscv#47 · Filter by author Jaswanthj006 opened on Oct 13, 2026

• Sv32 page walk accepts a misaligned megapage (level-1 leaf with PPN[0] != 0) instead of faulting

  ultraembedded/biriscv#46 · Filter by author CacheGuruinthemaking opened on Sep 16, 2026

• sstatus stores and reads back UIE/UPIE although the N extension is absent

  ultraembedded/biriscv#45 · Filter by author CacheGuruinthemaking opened on Sep 16, 2026

• sip and sie are not masked by mideleg: non-delegated M-level bits are visible to S-mode

  ultraembedded/biriscv#44 · Filter by author CacheGuruinthemaking opened on Sep 16, 2026

• S-mode can set and clear sip.SEIP and sip.STIP

  ultraembedded/biriscv#43 · Filter by author CacheGuruinthemaking opened on Sep 16, 2026

• mstatus.TVM is stored and reads back as 1, but S-mode satp access and SFENCE.VMA never trap

  ultraembedded/biriscv#42 · Filter by author CacheGuruinthemaking opened on Sep 16, 2026

• mstatus.TSR is stored and reads back as 1, but SRET in S-mode is never trapped

  ultraembedded/biriscv#41 · Filter by author CacheGuruinthemaking opened on Sep 16, 2026

• No mcounteren/scounteren: U- and S-mode can always read cycle/time

  ultraembedded/biriscv#40 · Filter by author CacheGuruinthemaking opened on Sep 16, 2026

• mepc/sepc bits [1:0] are stored and used although IALIGN=32

  ultraembedded/biriscv#39 · Filter by author CacheGuruinthemaking opened on Sep 16, 2026

• medeleg[11] (environment call from M-mode) is writable and reads back as 1

  ultraembedded/biriscv#38 · Filter by author CacheGuruinthemaking opened on Sep 16, 2026

• Interrupt cause priority is inverted: the external interrupt has the lowest priority

  ultraembedded/biriscv#37 · Filter by author CacheGuruinthemaking opened on Sep 16, 2026

• stvec / mtvec store reserved MODE values, and the trap target includes the MODE bits

  ultraembedded/biriscv#36 · Filter by author CacheGuruinthemaking opened on Sep 13, 2026

• mip.MEIP / MTIP / MSIP are software-writable, so software can raise machine interrupts

  ultraembedded/biriscv#35 · Filter by author CacheGuruinthemaking opened on Sep 13, 2026

• MRET/SRET to a mode below M does not clear mstatus.MPRV

  ultraembedded/biriscv#34 · Filter by author CacheGuruinthemaking opened on Sep 13, 2026

• mstatus.MPP accepts reserved value 2'b10; MRET then puts the hart in privilege level 2

  ultraembedded/biriscv#33 · Filter by author CacheGuruinthemaking opened on Sep 13, 2026

• misa does not report S or U when SUPPORT_SUPER=1

  ultraembedded/biriscv#32 · Filter by author CacheGuruinthemaking opened on Sep 13, 2026

• SDK environment

  ultraembedded/biriscv#26 · Filter by author chengquan opened on Oct 14, 2024
  4

• Boot RISC-V Linux Failed, ERROR: Invalid opcode: 30529073 at PC: 8040016c

  ultraembedded/biriscv#25 · Filter by author RonxBulld opened on Oct 3, 2023

• Wrong opcode for CSR_MCYCLE, CSR_MTIME and CSR_MTIMEH

  ultraembedded/biriscv#24 · Filter by author Gianluke27 opened on Sep 23, 2023

• FPGA Implementation

  ultraembedded/biriscv#23 · Filter by author SB308 opened on Sep 15, 2023

• undefined reference to `VlThreadPool::VlThreadPool(VerilatedContext*, unsigned int)'

  ultraembedded/biriscv#22 · Filter by author samuelyenyen opened on Aug 30, 2023
  3

• make failed...error

  ultraembedded/biriscv#20 · Filter by author crayon7442 opened on Apr 16, 2023
  1

• Operating Frequency

  ultraembedded/biriscv#19 · Filter by author anandmay22 opened on Aug 19, 2022
  1

• Consider taping out core on SKY130 open source process with no cost shuttle program?

  ultraembedded/biriscv#18 · Filter by author mithro opened on Apr 12, 2022

• Consider adding biriscv to LiteX CPU ecosystem?

  ultraembedded/biriscv#17 · Filter by author mithro opened on Apr 12, 2022