Verilator open-source SystemVerilog simulator and lint system
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Nov 9, 2026 - SystemVerilog
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verilog-simulator
Here are 23 public repositories matching this topic...
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
python toolchain documentation fpga sphinx primitives verilog synthesis lattice hdl xilinx-fpga ice40 artix7 artix vpr kintex7 architecture-definitions verilog-simulator symbiflow verilog-simulations
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Nov 5, 2026 - Jupyter Notebook
5-stage pipelined 32-bit MIPS microprocessor in Verilog
verilog microprocessor computer-architecture microprocessors verilog-hdl mips-architecture mips-processor bits-pilani computer-organization verilog-components verilog-snippets mips-instructions computer-organisation verilog-programs verilog-simulator verilog-project
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Apr 3, 2020 - Verilog
A place to keep my synthesizable verilog examples.
simulator asic fpga hardware waveform verilog xilinx synthesis vivado systemverilog gtkwave hdl iverilog hardware-description-language verilog-simulator asic-design synthesize hardware-architecture
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May 19, 2026 - Verilog
the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
traffic verilog vivado verilog-hdl traffic-light traffic-sign-recognition vivado-hls verilog-programs verilog-simulator verilog-project verilog-code vivado-simulator
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Jul 18, 2020 - JavaScript
Hardware description of a complete Ballot Box made in Verilog with implementation in FPGA-Altera-DE-2-155, made in Verilog with Quartus Prime in discipline ISL for computer science graduation.
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Apr 25, 2019 - Verilog
Example to control VCS simulation with a C/C++ program. This involves VCS output a shared object instead of an executable (simv).
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Mar 5, 2020 - Makefile
The Logic Simulator is an advanced tool designed to facilitate the understanding of sequential circuit design. This application implements fundamental concepts of computer architecture and digital systems engineering through an intuitive drag-and-drop interface, providin
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Aug 5, 2025 - JavaScript
A playground based on the classic version of the Cloud V IDE
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Mar 23, 2021 - JavaScript
32-bits MIPS Processor with 5-stage pipeline
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May 16, 2021 - Verilog
build verilator with zig
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Jun 6, 2026 - Zig
"Repository containing a collection of Verilog code modules and test bench for digital design projects. "
counter encoder decoder verilog alu multiplexer comparator testbench verilog-hdl gates 7segment shiftregister verilog-programs verilog-simulator verilog-project testbench-generator-verilog
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Apr 1, 2024 - Verilog
Digital System Design Verilog Implementation
verilog logic-gates fifo lifo adders verilog-simulator subtractor verilog-code digital-system-design
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Feb 26, 2022 - Verilog
Finished. Plans to pipeline and implement on fpga in future. NTS - Push immediate gen update for default case.
students custom verilog isa student-project verilog-hdl instruction-set-architecture risc-v riscv32 verilog-simulator verilog-project verilog-code
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Jul 23, 2026 - Verilog
Designing Basic-to-advanced verilog projects
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Oct 28, 2026 - SystemVerilog
Computer Architecture Lab Course 2022/1400, Fall CSE & IT Dept., Shiraz University
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Feb 4, 2022 - Verilog
Implementasi Verilog dari game Snake klasik untuk FPGA dengan output VGA. Mencakup testbench ModelSim dan laporan sintesis ASIC Qflow.)
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Mar 27, 2026 - Verilog
A verilog program that mimics the circuitry of a 4-bit register implemented with four 4x1 multiplexers and four D-Flipflops
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Oct 30, 2021 - Verilog
Mixed Language HDL simulator frontend for NVC
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Nov 8, 2026 - C++
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