Compact and Efficient RISC-V RV32I[MAFC] emulator
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Updated
Nov 2, 2026 - C
Compact and Efficient RISC-V RV32I[MAFC] emulator
A 5-stage pipelined RV32IMF RISC-V SoC optimized for FPGA (Nexys Video/4-DDR). Features a custom IEEE-754 FPU, interrupt-driven UART, and various peripherals.
Web-based RISC-V (RV32IMF) SoC simulator & assembler — CPU, MMU, cache, TileLink bus, DMA and peripherals, for learning computer architecture.
A custom RISC-V (RV32IMF) soft-core, "Hornet", implemented on Artix-7 FPGA for Edge AI and Network Intrusion Detection.
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