cmos-circuits

微电子和集成电路自学指南

Designed and simulated all fundamental and universal CMOS logic gates (NOT, AND, OR, NAND, NOR, XOR, XNOR) using the Electric VLSI Design Tool. This project includes schematic design, DRC-clean layouts, ALS simulation, and waveform analysis.

Converting Boolean expressions to CMOS Circuits

Design and Layout implementation of a high-performance two-stage Operational Amplifier (OPAMP) using180nm semiconductor technology. Achieved required gain, bandwidth, and power efficiency through simulation and characterization.

This repository contains a CMOS inverter circuit designed and simulated using LTspice. A CMOS inverter which is actually a "Hello World" in VLSI design logic is a fundamental building block in digital electronics, and this project aims to showcase its operation and characteristics.

A project for designing and implementing TTL to CMOS and CMOS to TTL interfacing in a microcontroller environment using NGSPICE. The code includes simulations and analysis of signal behaviour across different logic families.

FPGA-implemented RISC-V processor, evolved from single-cycle to 5-stage pipelined architecture for higher performance and timing efficiency. BRAM-based instruction memory optimizes FPGA usage. Fully FPGA-ready, general-purpose yet tailorable for any AI application, demonstrated with an ML heart rate anomaly detector for wearable AI.

This repository contains a python script which converts a Boolean Expression to a .sim file.

This repository contains some the codes to simulate various operations and characteristics of MOS circuits

Designing JK Flip-Flop CMOS using Synopsys Custom Compiler.

Performed power analysis of a half subtractor circuit using parametric analysis for 180nm technology with Cadence Virtuoso

FuzzyMSFLA-Algorithm (Fuzzy adaptive optimisation method)

This project demonstrates the complete design, layout, simulation, and verification of a **CMOS Inverter** using the **Electric VLSI Design Tool**.

FuzzyACOR-Algorithm (Adaptive fuzzy metaheuristic based optimisation algorithm)

A github pages site to generate diagrams of tables for a given logical expression

This repository contains all the experiments which I have done on LTSpice software for the VLSI Design course.

This repository contains the design, simulation, and performance evaluation of a CMOS NAND Gate using Cadence Virtuoso. The project highlights the design principles and operational characteristics of a fundamental digital logic gate implemented with CMOS technology.

Using a pulse wave as an input referencing as clock we try to generate three different pulses having different pulse width

In this repository, there are designs and simulations for VLSI chip projects based on simple CMOS logic circuits and gates, created using the Microwind tool.

Omni Quantum Dual Helix Core (OQ-DHC) v8.6: 8-Layer Tensor-Rechenkern & polygonfreie Lichtfeldsynthese (GTR). CMOS Fusion Features: Asynchrones Hardware-Gating auf Transistor-Ebene via S.W.A.T. Interlock, digitaler Grafik-Zwilling & O(1) Cross-Layer Formel-Modulation zur Elimination von Signal-Leakage.