All pull requests

Pull requests

• [ESI][BSP] Connect engines' hostmem_read_list ports in ChannelEngineService

  #11300·teqdruid opened Oct 15, 2026Contributor·

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  1

• [MooreToCore][Sim] Add lowering for substring

  #11299·Beanie496 opened Oct 15, 2026·

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• [LLHD] Combinational cycle bug fix

  #11298·garikmirakyan06 opened Oct 15, 2026·

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• [SV] Add sv.var_assign driver lint pass

  #11294·okekayode opened Oct 14, 2026Contributor·

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  7

• [SV] Remove SystemVerilog interface support

  #11293·teqdruid opened Oct 14, 2026Contributor·

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  1

• [Stacked on #11238] Support sequential user-defined primitives (UDPs) in circt::ImportVerilog (edge-sensitive/sync-row only).

  #11289·qiaozhang-pr opened Oct 13, 2026Contributor·

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  5

• [Comb] Fold single-bit extract of add with constant low bits into icmp.

  #11288·dma14 opened Oct 13, 2026Contributor·

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  2

• [Comb] Narrow shl to highest demanded bit when shift upper bits are 0

  #11287·dma14 opened Oct 13, 2026Contributor·

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  2

• [Comb] Narrow trailing bits of add and sub when carry/borrow-free.

  #11286·dma14 opened Oct 13, 2026Contributor·

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  10

• [ESI][Runtime] Add a DRAM service implementation and cosim DRAM model

  #11274·teqdruid opened Oct 10, 2026Contributor·3/3·

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  2

• [PyCDE] Add the esi.Dram standard service

  #11273·teqdruid opened Oct 10, 2026Contributor·2/3·

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  2

• [ESI] Add a DRAM standard service declaration

  ESI
  #11272·teqdruid opened Oct 10, 2026Contributor·1/3·

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  2

• [HW] ArrayGetOp::fold: leave a constant out-of-range index unfolded

  #11271·bdwoods83 opened Oct 9, 2026·

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  4

• [LLHD] Unroll loops with early exits, do-while, and any constant compare

  #11270·bdwoods83 opened Oct 9, 2026·

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• [MooreToCore] Lower ==?, ===, case and casez against X/Z constants

  #11269·bdwoods83 opened Oct 9, 2026·

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• [ImportVerilog] Decide case exhaustiveness by distinct label values

  #11268·bdwoods83 opened Oct 9, 2026·

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  1

• [MooreToCore] Range-check dynamic array element accesses

  #11267·bdwoods83 opened Oct 9, 2026·

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  1

• [Comb] Fix a dangling condition in foldCommonMuxValue

  #11261·bdwoods83 opened Oct 9, 2026·

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  1

• [Sim] Add operations on Variant values

  #11248·fzi-hielscher opened Oct 7, 2026Contributor·

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  1

• [FIRRTLToHW] Emit error for integer widths exceeding IntegerType max

  #11246·viniciusfdasilva opened Oct 7, 2026·

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  9

• [PIR] Add clocking operations

  #11241·dobios opened Oct 6, 2026Member·

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  4

• [FIRRTL][InferDomains] Support bottom-up inference

  #11240·maerhart opened Oct 6, 2026Member·

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  1

• [FIRRT] Treating cases without body on firrtl

  #11234·viniciusfdasilva opened Oct 4, 2026·

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  3

• [HW] Unwrap bitcasts and concats into array_create

  #11233·jpienaar opened Oct 4, 2026Member·

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  4

• [ImportVerilog] Support tran/tranif0/tranif1 switch primitives

  #11220·mafeguimaraes opened Oct 2, 2026Contributor·

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  28