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[TIRx] Store tensor address geometry in layouts - #20786
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Make layouts the single source of tensor address geometry while retaining constructor adapters and regular-memory ABI matching. Preserve compact stride matching, post-swizzle origins, and layout-aware view and lowering semantics across TIRx and S-TIR.
spectrometerHBH
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Oct 18, 2026
Keep memory contiguity on TileLayout and let TensorType prove default shape coverage and zero origin. Reuse optional analyzers lazily across both predicates and preserve origin-independent packing and footprint behavior.
tqchen
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Oct 18, 2026
Make layout the single source of tensor strides and element offsets. Tensor and S-TIR declarations accept explicit layouts, while views forward layout geometry directly. Shape-aligned memory layouts support dynamic strides and linear offset expressions through the existing parameter binder. Provide structural shape/stride matching and distinguish TileLayout contiguity from TensorType default shape coverage and zero origin. Both predicates reuse an optional analyzer after deep-equality checks. Python exposes the optional named matching result only in S-TIR. Shared-memory pools select their physical allocation base with pointer offsets, and Relax preserves contiguous native tensor origins at call boundaries.
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Make layout the single source of tensor strides and element offsets. Tensor and S-TIR declarations accept explicit layouts, while views forward layout geometry directly. Shape-aligned memory layouts support dynamic strides and linear offset expressions through the existing parameter binder.
Provide structural shape/stride matching and distinguish TileLayout contiguity from TensorType default shape coverage and zero origin. Both predicates reuse an optional analyzer after deep-equality checks. Python exposes the optional named matching result only in S-TIR. Shared-memory pools select their physical allocation base with pointer offsets, and Relax preserves contiguous native tensor origins at call boundaries.