The Silis Foundation is an open-source hardware and digital design research organization behind Silis, an Integrated Development Environment (IDE) engineered for the complete RTL-to-GDSII ASIC silicon design flow.
Beyond EDA toolchain unification, the foundation conducts empirical digital design research, microarchitectural benchmarks, and hardware/software co-design—exploring spatial compute fabrics (such as systolic tensor arrays), custom RISC-V coprocessor extensions (GEMMrv32), and bare-metal runtime infrastructures for their own open silicon.
- Silis IDE — Flagship modular open-source RTL-to-GDSII ASIC design environment integrating Yosys, OpenROAD, OpenSTA, and Magic VLSI with native C++ layout parsing engines bound via pybind11.
- GEMMrv32 — Spatial 8×8 systolic-array coprocessor integrated into the NEORV32 RISC-V Custom Functions Subsystem (CFS) for accelerated matrix compute with ping-pong tiling registers.
- PulseGEMM — 16×16 INT8 systolic compute accelerator on Microchip PolarFire SoC with 64-bit AXI4-DMA and Linux UIO drivers (256 MACs/cycle).
- DOOM on GEMMrv32 — Bare-metal OS-less port of DOOM offloading 3D transformation matrices directly to systolic hardware coprocessors.
- GEMMrvStudio — Telemetry, simulation profiling, and verification environment for custom RISC-V coprocessors.
- Jerome Antony Robin (@JeromeAntonyRobin) — Lead Developer
- Eatheswar N (@eatheswar) — Lead Developer
- Physical Design Automation: Sub-millisecond DEF layout decoding, interactive clock-tree visualization, and automated tapeout pipelines.
- Custom Silicon Architectures: Domain-specific ISA coprocessor extensions, custom execution units, and spatial PE grids.
- Hardware/Software Co-Design: Bare-metal runtimes, userspace DMA interfaces, and zero-overhead memory streaming for edge silicon.
