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  • Set programming language of Verilog code for correct syntax highlighting

    @piegamesde piegamesde committed Nov 24, 2019
    1a41856

  • Updated The Basics (markdown)

    @redpanda3 redpanda3 committed Oct 18, 2018
    aeb6858

  • Update filename to reflect source

    @aksell aksell committed Jul 8, 2018
    825e242

  • Update filename to reflect source

    @aksell aksell committed Jul 8, 2018
    5cb6c08

  • Bring Wiki stuff up to date - Show --backend-name verilator method for launching - Fix what test_run_dir paths look like using run scripts

    @chick chick committed Sep 29, 2017
    1eceddc

  • Remove parens from asUInt casts; add reset.toBool; use dev branches for code checks.

    @ucbjrl ucbjrl committed Sep 14, 2017
    0692d7f

  • Chisel3 syntax fixes.

    @ucbjrl ucbjrl committed Sep 12, 2017
    5335b79

  • Updated The Basics (markdown)

    @ucbjrl ucbjrl committed Sep 12, 2017
    18787de

  • Updated The Basics (markdown)

    @ucbjrl ucbjrl committed Sep 12, 2017
    1cf9757

  • typo

    @schoeberl schoeberl committed Aug 28, 2017
    0d33461

  • Clearify that when is a multiplexer and only when the assignment destination is a register the Verilog comparison is valid.

    @schoeberl schoeberl committed Aug 28, 2017
    7fdfe54

  • typo

    @schoeberl schoeberl committed Aug 27, 2017
    cfc25cc

  • Updated The Basics (markdown)

    @schoeberl schoeberl committed Aug 27, 2017
    a4838a5

  • mention RegNext

    @schoeberl schoeberl committed Aug 27, 2017
    cb4aede

  • Updated The Basics (markdown)

    @schoeberl schoeberl committed Aug 27, 2017
    1f66b37

  • Updated The Basics (markdown)

    @chick chick committed Apr 27, 2017
    dc7ea36