Show & Tell: Synapse-RV — Tapeout-Ready 64-bit RISC-V SoC with 8x8 Systolic Array NPU (Sky130)

[Anupam Maji (Aizen-9000)]

Hi RISC-V Community,
I wanted to share my completed physical design project, Synapse-RV. It is an independent, tapeout-ready Edge AI System-on-Chip (SoC) designed for highly power-constrained machine learning workloads under 1W.
The physical design is fully verified and tapeout-ready. The architecture specifications, full pinout arrays, and validation metrics are publicly accessible via the datasheet repository here: https://github.com/Aizen-9000/synapse-rv
Architectural Highlights:

• Core Pipeline: Implements an RV64GC Linux-capable processor block connected via a 10-slave AXI4 crossbar matrix.
• Vector Extensions: Features an integrated RVV 1.0 Vector processing unit.
• AI Hardware Accelerator: Custom 8x8 Systolic Array NPU performing matrix-multiplication operations, delivering up to 12.8 GOPS @ 200MHz using INT8 precision.
• Fabrication Target: Hardened on the SkyWater 130nm open PDK (Sky130A).
• Physical Verification: 0 DRC violations via Magic; fully LVS clean across 2,884 nets via Netgen.
• System Peripherals: Integrated 4-channel DMA engine, dedicated L2 Cache controller, LPDDR4 controller, PCIe Gen2, and a hardware cryptographic secure boot system (AES-256/SHA-3).

The layout files (user_project_wrapper GDS blocks) are safely hosted offline on private infrastructure to protect the proprietary IP. This SoC block is available for commercial B2B licensing models.
I would love to connect with any developers, system integrators, or fabless groups in the ecosystem looking to evaluate an efficient edge-compute accelerator block! Feel free to reach out via GitHub or directly over email at majianupam173@gmail.com.